1. Field of the Invention
The present invention relates to a data transfer control apparatus which controls data transfer to be executed among a plurality of modules formed inside, for example, a system LSI.
2. Description of the Related Art
There has been known a data transfer control apparatus which is constructed inside a system LSI. This data transfer control apparatus has a plurality of bus interface units connected to a bus master via a master bus, and a plurality of bus slaves respectively connected to the bus interface units via a slave bus. The bus master is constituted by, for example, a DMA (Direct Memory Access) transfer controller. Each of the bus slaves is constituted by, for example, a RAM (Random Access Memory), an input/output module or the like.
The data transfer control apparatus executes data transfer from an input/output module or one bus slave to a RAM or another bus slave in the following manner. First, the DMA transfer controller or the bus master sends a request to a bus arbiter to acquire a bus access to access an input/output module, then fetches data from the input/output module over the slave bus, the bus interface unit and the master bus. Next, the DMA transfer controller sends a request to the bus arbiter to acquire a bus access to access the RAM, then transfers and writes the data, fetched from the input/output module, into the RAM.
Patent Document 1 (Japanese Patent Laid-Open No. 46538/1993) discloses, as a related art, a bus control system which has bus control means, intervened between a common bus and a microprocessor and an additional function circuit unit, for controlling transfer of data or a command on the common bus, issues a no-operation instruction to the microprocessor when the instruction of the microprocessor is fetched and transfers the fetched data or command to the additional function circuit unit without going through the microprocessor. This bus control system can carry out transfer of data or a command to the additional function circuit unit efficiently and eventually contribute to improving the system performance.
Patent Document 2 (Japanese Patent Laid-Open No. 210616/1993) discloses a computer device that has a ROM (Read Only Memory) to store instructions, RAM to store data, a CPU (Central Processing Unit) and an input/output device. The RAM is accessible to a peripheral circuit at the timing of fetching an instruction by the CPU or in an instruction fetch period so that the peripheral circuit can access the RAM without intercepting the execution of an instruction by the CPU via a bus for the RAM. Because the computer device can execute a DMA operation at the timing of instruction fetching in transferring data between the RAM and the peripheral device in the DMA system, execution of an instruction is not intercepted with, thus preventing contention of an access to the RAM by the CPU and the peripheral circuit.
Patent Document 3 (Japanese Patent Laid-Open No. 2002-7313) discloses a data processing device. In the data processing device, a master executes data exchange with individual modules on first and second external buses and executes data exchange among modules on the first and second external buses. The master sends a transmitting side and a receiving side address information via the external buses to allow a direct exchange of data among modules on the same external bus or different external buses. Through this structure, it permits communications among the individual modules via the minimum wiring of the buses and ensures an operation under low power consumption.
In case where the conventional data transfer control apparatuses perform data transfer, however, it is necessary to serially execute a sequence of operations, acquisition of a bus access, data reading, acquisition of a bus access, data writing, thus requiring multiple cock cycles to do those operations. As a result, data transfer unexpectedly takes a lot of time, thereby decreasing efficiency.